An NROM device is a nonvolatile read-only memory electronic memory device which stores charges in a dielectric layer and is well-known in the art. Referring to FIG. 1, there is shown a cross-sectional view of an NROM device 1 of the prior art. The device 1 is made on a silicon substrate 2 with a first conductivity type, and with first and second regions 3/4 spaced apart from one another which are of a second conductivity type different from the first conductivity type of the silicon substrate 2. Separating the first region 3 from the second region 4 is a channel region 5. A first insulating layer 6 such as silicon oxide or silicon dioxide is formed over the channel region 5. A dielectric 7, such as silicon nitride, is positioned over the silicon dioxide layer 6. A second insulating layer 8 such as another layer of silicon dioxide is positioned over the dielectric 7. Collectively, the first insulating layer 6, the dielectric layer 7 and the second insulating layer 8 are also known as an ONO layer 6–8. Finally, a polysilicon gate 9 is positioned on the second layer silicon dioxide 8. Thus, the dielectric 7 is spaced apart and is insulated from the channel region 5 via the first insulating layer 6. The polysilicon gate 9 is insulated and separated from the dielectric 7 by the second insulating layer of silicon dioxide 8. In summary, the polysilicon gate 9 is spaced apart and separated from the channel region 5 by the ONO layer 6–8.
The NROM device 1 is a double density, nonvolatile storage cell, capable of storing 2 bits of information in the cell. The polysilicon layer 9 serves as the gate and controls the flow of current between the first region 3 and the second region 4 through the channel region 5. To program one of the bits, the polysilicon gate 9 is raised to a high positive voltage. The first region 3 is held at or near ground and the second region 4 is raised to a high positive voltage. Electrons from the first region 3 accelerate into the channel 5 towards the second region 4 and through hot channel electron injection mechanism are injected through the first oxide layer 6 and are trapped in the dielectric 7 near the region 10 of the dielectric layer 7. Since the dielectric layer 7, comprising of silicon nitride is a nonconductive material, the charges are trapped in the region 10.
To program the other bit of the cell 1, the polysilicon layer 9 is raised to a high positive voltage. The second region 4 is held at or near ground and the first region 3 is raised to a high positive voltage. Electrons from the second region 4 accelerate in the channel 5 towards the first region 3 and through hot channel electron injection mechanism are injected through the first silicon dioxide layer 6 and are trapped in the region 11 of the dielectric layer 7. Again, since the silicon nitride layer 7 is nonconductive, the charges are trapped in the region 11.
To read one of the bits, the first region 3 is held near ground. A positive bias voltage is applied to the polysilicon layer 9. The voltage applied is such that if the region 11 does not contain trapped charges (i.e. is not programmed), it will cause the channel region 5 underneath it to be conductive. However, if the region 11 has trapped charges (i.e. is programmed), the channel region 5 underneath will not be conductive (not be turned on). A positive voltage is also applied to the second region 4. The voltage applied to the second region 4 is such that it causes a depletion region of the second region 4 to expand and encroach the channel region 5 so that it extends beyond the region 10. Thus, the state of whether region 10 is programmed or not is irrelevant in reading region 11 of the memory cell. Therefore, under that condition, the state of conduction of the channel 5 between the first region 3 and the second region 4 is dependent solely on the state of charge stored or trapped in the region 11.
To read the other bit, the voltages applied are simply reversed. Thus, the second region 4 is held near ground. A positive bias voltage is applied to the polysilicon layer 9. The voltage applied is such that if region 10 is not programmed, it will cause the channel region 5 underneath it to be conductive. However, if region 10 is programmed, channel region 5 underneath will not be conductive (not be turned on). A positive voltage is also applied to the first region 3. The voltage applied to first region 3 is such that it causes the depletion region of the first region 3 to expand and encroach into the channel region 5 beyond region 11 so that the state of charge stored or trapped in region 11 is irrelevant in reading region 10 of the memory cell.
To erase, the substrate 2, the first region 3, and the second region 4, may be connected to a high positive voltage thereby causing electrons from the trapped regions 10 and 11 to tunnel via Fowler/Nordheim tunneling into the substrate 2.
The problem with the NROM cell 1 of the prior art is that the channel 5 is on the planar surface of the silicon substrate 2, and channel region 5 needs to be sufficiently large so that the two trapped regions 10 and 11 are sufficiently separated. This becomes a problem as the cell 1 is scaled to smaller sizes, especially since the thickness of the ONO layers 6–8 cannot be scaled.
FIG. 2 illustrates another prior art design of a NROM device which stores charges in a dielectric layer, with a split gate memory cell configuration. Here, oxide and nitride layers 6–7, along with a memory gate electrode 8, are disposed over only a first section of the channel region 5. Also, the polysilicon gate 9 has a lower portion that is disposed over and insulated from a second section of the channel region 5 (via insulation material 12), and a second portion that extends up and over oxide 6, nitride 7 and memory gate 8. Electrical contacts 13 and 14 are formed to make electrical contact with first and second regions 3/4. With this configuration, only a single bit of information is stored by programming nitride layer 7 with trapped electrons, in the same manner as described above. The problem with this design is that is can be difficult to scale down in size. Specifically, the effective channel length needs to be long enough to tolerate different lithographic steps used to form the separate poly gate 9 and oxide 6/nitride 7/gate 8. Further, the width of the oxide/nitride/gate 6/7/8 is at least one lithographic feature length long, which is unnecessarily long given that the trapped charges are immobile within the dielectric material.
There is a need for an improved method of forming an electron trapping NROM device that allows the device to scale down further in size than conventional designs allow.